Memory System, FDV
Location of Job:
Mountain View, CA
General Description Vision:
Perform pre-silicon validation of higher levels of hierarchy of a new GPU IP.
Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers.
Review test plans of memory sub system (including L1c, l2c, acem); modify if necessary.
Write the tests outlined by test plan.
Enhance testbench if necessary, e.g. add coverage assertions. Leverage unit level verification infrastructure.
Debug test failures, fix test or testbench if necessary. Report RTL failures to RTL designers. Confirm bug is fixed.
Enhance test benches and tests to achieve coverage goals.
Apply formal methods to supplement stimulus based verification.
Support porting DUT and some testbench components to an emulation platform.
Experienced with verification methodology such UVM/VMM/OVM. UVM is preferred.
Experience verifying memory subsystem components like caches, mmu and/or SOC (e.g. CPU, GPU, DSP, Video Processor).
Understanding of micro-architecture and logic design fundamentals, e.g. caches, coherency, memory translation, page faults, etc.
Composed functional coverage assertions, preferably using system Verilog.
The qualified candidate will possess the following:
BSEE, or higher degree.
At least 5 years of experience in a design verification role.
Proficient in System Verilog. C++, Python/Perl skills are also desirable.
Good verbal and written communication skills.